Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a synchronous semiconductor memory device.
Description of the Related Art
A synchronous DRAM, one of the conventional synchronous semiconductor memory devices, comprises: a plurality of memory cells; a plurality of bit lines to which are respectively given potentials based on the data sent from the plurality of memory cells; a plurality of sense-amplifiers which respectively amplify the potential of the plurality of bit lines; and a plurality of column switches respectively connected between the plurality of bit lines and a plurality of data lines.
In the synchronous DRAM, the column-selection signal is given to sequentially select column switches, so that potentials based on the data of the memory cells that correspond to thus selected column switches are sequentially given to data lines.
The conventional synchronous DRAM sequentially outputs to the external the data based on a potential sent to the data line ,in response to the leading edge of the clock signal.
The conventional synchronous DRAM turns ON the column switches one by one to sequentially send to the data line a potential based on the data of mutually adjacent two memory cells, which therefore takes a considerably long time to do so.
With this, in the array configuration of the conventional synchronous DRAMs, in order to implement such a double-data-rate synchronous DRAM which outputs a potential based on the data of mutually adjacent two memory cells, it is necessary to lengthen the period of the clock signal, thus leading to a problem in that the DRAM cannot operate speedily.
Further, the synchronous DRAM includes in each memory block a great many sense-amplifiers. Those sense-amplifiers, each of which is connected to the power supply to activate itself, have mutually different distances between the power supply and themselves.
Therefore, the sense-amplifier most distant from the power supply suffers from a voltage droop due to a large wiring resistance between itself and the power supply.
This leads to decreases in the speed for the sense-amplifier to amplify the potential of bit lines, thus causing a problematical drop in the operational margin of the synchronous DRAM as a whole.